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PD - 94646
IRF7413Z
HEXFET(R) Power MOSFET
Applications l Control FET for Notebook Processor Power l Control and Synchronous Rectifier MOSFET for Graphics Cards and POL Converters in Computing, Networking and Telecommunication Systems Benefits l Ultra-Low Gate Impedance l Very Low RDS(on) l Fully Characterized Avalanche Voltage and Current
VDSS
30V
RDS(on) max
10m:@VGS = 10V
ID
13A
S S S G
1
8
A A D D D D
2
7
3
6
4
5
Top View
SO-8
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TA = 25C ID @ TA = 70C IDM PD @TA = 25C PD @TA = 70C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range
Max.
30 20 13 10 100 2.5 1.6 0.02 -55 to + 150
Units
V
c
A W
W/C C
Thermal Resistance
Parameter
RJL RJA Junction-to-Drain Lead Junction-to-Ambient
Typ.
--- ---
Max.
20 50
Units
C/W
f
Notes through are on page 10
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1
6/23/03
IRF7413Z
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
30 --- --- --- 1.35 --- --- --- --- --- 62 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.025 8.0 10.5 1.80 -5.0 --- --- --- --- --- 9.5 3.0 1.0 3.0 2.5 4.0 5.6 8.7 6.3 11 3.8 1210 270 140 --- --- 10 13 2.25 --- 1.0 150 100 -100 --- 14 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 15V ns nC nC VDS = 15V VGS = 4.5V ID = 10A S nA V mV/C A V m
Conditions
VGS = 0V, ID = 250A VGS = 10V, ID = 13A VGS = 4.5V, ID = 10A
V/C Reference to 25C, ID = 1mA
e e
VDS = VGS, ID = 250A VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 15V, ID = 10A
See Fig. 16 VDS = 15V, VGS = 0V VDD = 16V, VGS = 4.5V ID = 10A Clamped Inductive Load
= 1.0MHz
Avalanche Characteristics
EAS IAR Parameter Single Pulse Avalanche Energy Avalanche Current
d
Typ. --- ---
Max. 32 10
Units mJ A
Diode Characteristics
Parameter
IS ISM VSD trr Qrr ton Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- 24 16 3.1 A 100 1.0 36 24 V ns nC
Conditions
MOSFET symbol showing the integral reverse p-n junction diode. TJ = 25C, IS = 10A, VGS = 0V TJ = 25C, IF = 10A, VDD = 15V di/dt = 100A/s
e
e
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF7413Z
1000
TOP VGS 10V 8.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
1000
TOP VGS 10V 8.0V 4.5V 4.0V 3.5V 3.0V 2.8V 2.5V
100
BOTTOM
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
BOTTOM
10
10
1
2.5V
2.5V 20s PULSE WIDTH Tj = 150C
1
20s PULSE WIDTH Tj = 25C
0.1 0.1 1 10
0.1
1
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
2.0
RDS(on) , Drain-to-Source On Resistance
ID = 13A VGS = 10V
ID, Drain-to-Source Current ()
100
1.5
10
(Normalized)
T J = 150C
T J = 25C VDS = 10V 20s PULSE WIDTH
1.0
1 2 3 4 5 6
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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3
IRF7413Z
10000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
12.0 ID= 10A
VGS , Gate-to-Source Voltage (V)
10.0
VDS= 24V VDS= 15V
C, Capacitance(pF)
8.0
Ciss
1000
6.0
Coss
4.0
Crss
100 1 10 100
2.0
0.0 0 4 8 12 16
VDS, Drain-to-Source Voltage (V)
Q G Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
1000.00
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100.00 T J = 150C 10.00
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
10
100sec 1msec
1.00
T J = 25C
1 T A = 25C Tj = 150C Single Pulse 0.1 0 1 10 10msec
VGS = 0V 0.10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VSD, Source-to-Drain Voltage (V)
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF7413Z
14 12
ID, Drain Current (A)
2.5
VGS(th) Gate threshold Voltage (V)
10 8 6 4 2 0 25 50 75 100 125 150 T A , Ambient Temperature (C)
2.0
1.5
ID = 250A
1.0
0.5 -75 -50 -25 0 25 50 75 100 125 150
T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Ambient Temperature
Fig 10. Threshold Voltage vs. Temperature
100
D = 0.50
Thermal Response ( Z thJA )
10
0.20 0.10 0.05 0.02 0.01
J R1 R1 J 1 2 R2 R2 R3 R3 3 R4 R4 C 2 3 4 4
1
Ri (C/W)
1.8556 2.4927 25.570 20.340
P DM t1
i (sec)
0.000337 0.012752 0.691000 21.90000
1
0.1
Ci= i/Ri Ci i/Ri
0.01
SINGLE PULSE ( THERMAL RESPONSE )
t2 Notes: 1. Duty factor D = t 1/ t 2 2. Peak T J = P DM x Z thJA
0.001 1E-006 1E-005 0.0001 0.001 0.01 0.1
+T A
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF7413Z
140
EAS , Single Pulse Avalanche Energy (mJ)
15V
ID
TOP BOTTOM 3.1A 3.9A 10A
120 100 80 60 40 20 0 25 50 75 100
VDS
L
DRIVER
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
125
150
Starting T J , Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy vs. Drain Current
I AS
LD VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T
Current Regulator Same Type as D.U.T.
VGS Pulse Width < 1s Duty Factor < 0.1%
50K 12V .2F .3F
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VDS
90%
VGS
3mA
10%
IG ID
VGS
td(on) tr td(off) tf
Current Sampling Resistors
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF7413Z
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF7413Z
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* P =P loss conduction + P drive + P output
P = Irms x Rds(on) loss
+ (Qg x Vg x f )
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Ploss = (Irms x Rds(on ) )
2
Qgs 2 Qgd +I x x Vin x f + I x x Vin x f ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF7413Z
SO-8 Package Details
Dimensions are shown in millimeters (inches)
D A 5 B
DIM A b INCHES MIN .0532 .013 .0075 .189 .1497 MAX .0688 .0098 .020 .0098 .1968 .1574 MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00
A1 .0040
6 E
8
7
6
5 H 0.25 [.010] A
c D E e e1 H
1
2
3
4
.050 BASIC .025 BASIC .2284 .0099 .016 0 .2440 .0196 .050 8
1.27 BAS IC 0.635 BAS IC 5.80 0.25 0.40 0 6.20 0.50 1.27 8
6X
e
K L y
e1
A
K x 45 C 0.10 [.004] y 8X c
8X b 0.25 [.010]
A1 CAB
8X L 7
NOT ES : 1. DIMENS IONING & T OLERANCING PER AS ME Y14.5M-1994. 2. CONT ROLLING DIMENS ION: MILLIMET ER 3. DIMENS IONS ARE S HOWN IN MILLIMET ERS [INCHES ]. 4. OUT LINE CONFORMS T O JEDEC OUT LINE MS -012AA. 5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROT RUS IONS NOT T O EXCEED 0.15 [.006]. 6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUS IONS . MOLD PROT RUS IONS NOT T O EXCEED 0.25 [.010]. 7 DIMENS ION IS THE LENGT H OF LEAD F OR S OLDERING T O A S UBS T RAT E. 3X 1.27 [.050] 6.46 [.255]
FOOT PRINT 8X 0.72 [.028]
8X 1.78 [.070]
SO-8 Part Marking
EXAMPLE: T HIS IS AN IRF7101 (MOSFET ) DAT E CODE (YWW) Y = LAS T DIGIT OF T HE YEAR WW = WEEK LOT CODE PART NUMBER
9
INT ERNATIONAL RECT IFIER LOGO
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YWW XXXX F7101
IRF7413Z
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 ) 11.7 ( .461 )
8.1 ( .318 ) 7.9 ( .312 )
FEED DIRECTION
NOTES: 1. CONTROLLING DIMENSION : MILLIMETER. 2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES). 3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00 (12.992) MAX.
14.40 ( .566 ) 12.40 ( .488 ) NOTES : 1. CONTROLLING DIMENSION : MILLIMETER. 2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.62mH, RG = 25, IAS = 10A. Pulse width 400s; duty cycle 2%. When mounted on 1 inch square copper board.
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 06/03
10
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